1. Field of the Invention
The present invention relates to BEOL (back-end-of-line) metal interconnects in integrated circuits fabricated on semiconductor wafer substrates. More particularly, the present invention relates to a method of enhancing interface adhesion between adjacent layers, particularly between a low-k dielectric layer and an etch stop layer in BEOL metal interconnect formation.
2. Description of the Related Art
The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.
In the semiconductor industry, copper is being increasingly used as the interconnect material for microchip fabrication. The conventional method of depositing a metal conducting layer and then etching the layer in the pattern of the desired metal line interconnects and vias cannot be used with copper because copper is not suitable for dry-etching. Special considerations must also be undertaken in order to prevent diffusion of copper into silicon during processing. Therefore, the dual-damascene process has been developed and is widely used to form copper metal line interconnects and vias in semiconductor technology. In the dual-damascene process, the dielectric layer rather than the metal layer is etched to form trenches and vias, after which the metal is deposited into the trenches and vias to form the desired interconnects. Finally, the deposited copper is subjected to chemical mechanical planarization (CMP) to remove excess copper (copper overburden) extending from the trenches.
A typical dual damascene process is shown in the cross-sectional views of FIGS. 1A-1D. The process is carried out on a substrate 100 on which a conductive metal layer 102 is deposited. A bottom dielectric layer 104, an etch stop layer 106 and an upper dielectric layer 108 are sequentially formed on the substrate 100. A photoresist layer 110 is then formed over the upper dielectric layer 108. Photolithography techniques are then used to pattern the photoresist layer 110 for subsequent formation of a via opening in the photoresist layer 110.
The photoresist layer 110 is used as an etching mask as the upper dielectric layer 108, the etch stop layer 106 and the bottom dielectric layer 104 are sequentially etched to form a via opening 112 through which the metal layer 102 is exposed, as shown in FIG. 1B. The photoresist layer 110 is removed and a second photoresist layer 114 is formed on the substrate 100, as shown in FIG. 1B. Photolithography techniques are then used to pattern the photoresist layer 114 for formation of a trench above the via opening 112.
The photoresist layer 114 is used as an etching mask and the etch stop layer 108 as an etch stop as the upper dielectric layer 108 is etched to form a trench 116 over the via opening 112, as shown in FIG. 1C. The photoresist 114 is subsequently removed. Finally, as shown in FIG. 1D, a metallic layer 118 is deposited into the via opening 112 and overlying trench 116. The metallic layer 118 is subjected to chemical mechanical planarization (CMP) for the purpose of planarizing or smoothing the upper surface of the metallic layer 118.
When the gate length of ICs is less than about 0.18 mm, the propagation time or delay time is determined by interconnect delay rather than device gate delay. To address this problem, new materials with low dielectric constants (k) are being developed for use as dielectric layers in IC fabrication. The aim of this development effort is to reduce time constant (RC delay), power consumption and cross-talk in ICs. This development effort increases in importance as the gate length of ICs approaches 0.09 mm and beyond.
There are two basic groups of low-k dielectric materials: the traditional inorganic group, which includes silicon dioxide; and the newer group of organic polymers, which includes poly-para-xylene. Organic polymers are considered an improvement over inorganic low-k dielectric materials because the dielectric constant of organic polymers can be as low as 2.0. However, most of the currently-available organic polymers suffer from several disadvantages, including insufficient thermal stability and fragility.
While it is well-suited for planarization if the correct slurry and process parameters are used, CMP may induce physical stresses in the substrate, leading to cracking and peeling of dielectric layers, particularly at the interface of the upper dielectric layer with the etch stop layer. Moreover, due to the increasingly widespread usage of fragile low-k dielectric materials, CMP may result in shearing or crushing of these layers. In addition, stresses applied to the low-k dielectric layer during chip packaging can induce peeling and cracking of the layer.